1. Field of the Invention
The present invention relates to an apparatus for conditioning signals in a computer system, and more particularly to an apparatus for conditioning signals input to a computer system board to determine system board compatibility with bus timing specifications.
2. Description of the Related Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. A driving force behind the success of the personal computer industry has been the concern on the part of system designers to maintain compatibility between the newer computer systems that are being developed and the older systems that are currently on the market or in use. Many of the compatibility problems that arise in the design of computer systems result from the necessary timing considerations between the various components within the system and the external input/output (I/O) devices that are connected to the system. Communication between the various components and external I/O devices is possible via a system bus, which is essentially an electrical highway connecting the various elements of the computer together. In a computer system, the system bus resides on the computer system board. Timing considerations require that the timing of the operations on this bus must be suitably matched to facilitate the exchange of signals between devices on the bus. The timing between the various elements of the computer system must be synchronized in order for them to be able to communicate with each other and to allow for the proper functioning of the computer system.
In order to maintain backwards compatibility with previous computer systems and software, de facto standard bus architectures have emerged in personal computer systems. One of the standard bus architectures in the personal computer industry is the bus architecture introduced in the International Business Machines Corp. (IBM) PC/AT personal computer, now referred to as the Industry Standard Architecture (ISA). An extended version of this bus architecture has recently been developed, which is referred to as the Extended Industry Standard Architecture (EISA). EISA includes a 32-bit address bus, a 32-bit data bus, and was designed to include full backwards compatibility with all ISA devices and software. In order to provide full testing capabilities to EISA system boards and ensure that these boards actually conform to EISA specifications, an apparatus is needed to verify functional and timing compatibility of EISA system boards.
Background on the ISA and EISA bus architectures is deemed appropriate. IBM's first personal computer, the IBM PC, included an 8 bit data bus and twenty address lines, referred to as the SA&lt;19..0&gt; address lines. However, as the personal computer industry developed, the need for greater amounts of memory became apparent. Therefore, IBM introduced the IBM PC/AT personal computer, which included 24 address lines and 16 data lines. These new address lines were achieved by including seven new latched address lines in the architecture referred to as the LA&lt;23..17&gt; address lines. The latched or LA address lines were developed to take advantage of the faster memory speeds that were available. However, the need for greater amounts of memory, as well as increased data bandwidth, continued to grow, and this need has culminated in EISA. EISA includes a 32 bit data bus, a 32 bit address bus, and retains full backward compatibility with the ISA.
The EISA system bus provides Standard, Compressed, and Burst cycle types for data transfers between the microprocessor and memory or I/O slaves. EISA bus masters may use Standard and Burst cycles, but may not use Compressed cycles. Compressed cycles complete one transfer each 11/2 BCLK signal period and are used by the microprocessor to transfer data to or from fast EISA memory or I/O slaves. Burst cycles are zero-wait-state transfers to or from EISA memory which provide a continuous sequence of 1 BCLK read or write cycles. The first data transfer of a Burst Cycle is identical to a normal or Standard EISA cycle. In subsequent Burst Cycles, data is asserted at every falling edge of the BCLK signal because the data is latched on the following rising edge.
The EISA specification requires that a slave card assert one of the following signals, if it is not the default size (8-bit), to indicate the data bus width and general timing it can support: EX32*, EX16*, IO16*, or M16*. An EISA memory or I/O slave asserts EX32* or EX16* to indicate that it supports 32 bit (dword) or 16 bit (word) transfers, respectively. An ISA memory or I/O slave asserts M16* or IO16*, respectively, if the slave has a 16 bit data bus size. An EISA slave card can influence the type of cycle used by asserting the SLBURST* or NOWS* signals. An EISA slave asserts the SLBURST* signal to indicate that it is capable of performing Burst transfers. The NOWS* signal has a different meaning for EISA cycles than for ISA cycles. In EISA transfers, the NOWS* signal indicates that the slave is capable of supporting Compressed cycles. For ISA cycles, the NOWS* signal determines the number of BCLK signal cycles that are required by the slave. The number of wait states which occur during a cycle is controlled exclusively by a slave. An EISA slave negates the EXRDY signal to request wait state timing. An ISA slave negates the CHRDY signal to request wait states and asserts the NOWS* signal to indicate that additional clock cycles are not required.
Computer systems developed around the ISA bus utilize the SA&lt;1&gt; and SA&lt;0&gt; address lines to distinguish between respective 8 bit quantities or bytes being accessed in I/O memory. The ISA bus also includes a signal referred to as SBHE*, which indicates when asserted low that expansion cards which support 16 bit data transfers should drive or receive data on the high half of the D&lt;15..0&gt; or 16 bit data bus. In contrast, the EISA bus includes four byte enable signals referred to as BE&lt;3..0&gt;* which distinguish between respective bytes of data being accessed. The BE&lt;3..0&gt;* signals allow a CPU or EISA bus master to individually access any of the respective bytes residing in the respective dword data structures in memory.
As previously discussed, EISA maintains full backwards compatibility with all ISA devices and software. In order to provide this compatibility, EISA computer systems include logic which allows EISA and ISA devices to talk with each other. This logic is implemented in a chip referred to as the EISA Bus Controller or EBC. The EBC monitors the EISA bus and performs the appropriate bus cycle conversions between ISA and EISA bus cycles. The EBC includes data translation logic to allow EISA expansion cards, which generally include either a 16 bit or 32 bit data size, to operate properly with ISA expansion cards, which include either a 16 bit or 8 bit data size. In performing data translations, the EBC performs signal translations between the BE*&lt;3..0&gt; signals and the SA&lt;1..0&gt; and SBHE* signals, where appropriate. The EBC also performs translations between the EISA cycle control signals CMD*, W-R and M-IO and the ISA command signals MRDC*, MWTC*, IORC*, and IOWC*. Therefore, the EBC performs ISA/EISA bus cycle and data translations to enable ISA and EISA bus masters and slaves with varying data sizes to interface with each other and to the host processor.
During bus master cycles, the EBC tracks the bus cycles being performed and performs the necessary translations between the EISA and the ISA control signals, as described above. It also detects data size mismatch conditions that require it to take control of the bus and run additional cycles. For example, if a 32 bit EISA bus master is attempting to perform 32 bit data transfers to a 16 bit ISA slave, the EBC would automatically translate the EISA signals into ISA signals. It would also break up the 32 bit transfer into two 16 bit transfers to/from the ISA slave. On write transfers, the EBC stores the high order word written by the bus master while the low order word is being transferred to the slave. It would then change the appropriate address lines and copy the high order word written by the bus master to the low order byte lanes and complete the second transfer. On a read transfer, the EBC would, after completing the proper translations, latch the 16 bits from the slave and initiate another transfer. It would change the appropriate address line to point to the next word from the slave and latch the 16 bits of data received. It would then reassemble the data read in the two 16 bit reads into one 32 bit dword, drive the 32 bits of data onto the data bus, and assert the EX32* signal, signalling the bus master to latch the 32 bit dword present on the data bus.
At the trailing edge of the START* signal, 16 and 32 bit EISA bus masters sample the EX32* signal to determine if the accessed slave supports 32 bit EISA transfers. A 16 bit EISA bus master also monitors the EX16* and EX32* signals to determine if the accessed slave supports 16 bit EISA transfers. For 32 bit bus masters, the asserted EX32* signal indicates that the accessed slave supports 32 bit EISA transfers, and the negated EX32* signal indicates that the EBC must perform data size translation. For 16 bit bus masters, the asserted EX16* or EX32* signal indicates that the accessed slave supports 16 bit EISA transfers, and the negated EX16* (and EX32*) signal indicates that the EBC must perform data size translation. When the respective EX32* or EX16* signals are negated, the bus master tri-states its BE&lt;3:0&gt;* signal outputs, the START* signal, and its data lines to allow the EBC to take control of the bus and generate its own BE&lt;3:0&gt;* signals and START* signal and drive the data bus during write operations.
In instances where a 16 bit bus master is performing a write operation to an odd address of a 32 bit slave, the EBC may perform a data copying operation from the low order to high order bytes of the data bus to enable the 32 bit slave to receive its data on the high order bytes of the data bus. In this instance, the EBC receives the first 16 bit data transfer and copies this data to the high bytes of the data bus. Also, when a 32 bit bus master is receiving data from an 8 bit or 16 bit slave, the EBC performs data copying from the low order bytes to the high order bytes to enable the bus master to receive a 32 bit transmission.
32 bit EISA bus masters may optionally "downshift" to a 16 bit size to perform Burst cycles with a 16 bit EISA slave. When a 32 bit EISA bus master is downshifting, it asserts the MASTER16* signal while the START* signal is asserted to disable the automatic 32 to 16 bit data size translation performed by the EBC for 16 bit EISA memory Burst slaves. Upon detecting a downshift, the EBC will not take control of the bus, but will allow the bus master to do its own byte masking.
Another difference between the ISA and EISA architectures is that the ISA bus includes four signals referred to as MRDC*, MWTC*, IOWC*, and IORC* to differentiate between memory or input/output (IO) cycles and read or write cycles. In contrast, EISA includes signals referred to as W-R and M-IO to differentiate between write/read and memory/IO cycles, respectively. The W-R and M-IO signals are unique in that they each have three distinct states: asserted, negated or tri-stated.
For more information on EISA signals and cycle types, please refer to the EISA specification, Version 3.1, which is included in this application as Appendix 1.